One complete source period; RMS includes DC.
Circuit and current path
T₁/T₂/T₃ connect U/V/W to +. T₄/T₅/T₆ return current from − to U/V/W. The source block supplies the balanced phase voltages; its neutral N is not connected to the load. Wire crossings without a dot are separate conductors. Every gate driver returns locally to its SCR’s K.
Each sine-wave circle is an AC phase source. The sources share the internal star point N; vU, vV, vW are phase-to-neutral voltages. Only U, V and W connect to the bridge: there is no neutral wire.
Fixed arrows define positive references. Teal paths carry rectifier current; the purple resistor and brown capacitor branches have their own currents. Scroll the diagram at readable size or use Fit diagram.
Steady-state waveforms
Source and output voltages
Load and source currents
io enters the complete load. For R‖C, the dashed purple iR is the resistor current and solid brown iC is the capacitor-branch current: io = iR + iC. Coincident traces are drawn at their true values.
Gate commands and actual conduction
The logical gate traces use 0/1. Filled lower strips mark actual conduction of each SCR, independently of the gate command. All panels share the probe; click or drag within a waveform to move it.
Filtering and branch currents
Actual conduction intervals
Angles are measured in the full source period. Each end is an actual extinction or commutation, independent of gate removal. For the half-wave SCR, the end of its source interval is β; a freewheeling diode can then carry the load current.
Ripple = AC RMS / absolute mean, calculated about the actual mean. A zero mean makes the ratio undefined. Nominal pulse frequency describes the balanced periodic topology; a blocked output has no physical ripple.
Model and equations
During source conduction: L dio/dt + Rio + E = vo = upath − ndVF. Set L or E to zero when that series element is absent. During blocked intervals, io = 0 and vo = E.
For R‖C with RC > 0: iR = vo/R, iC = (vo − vC)/RC = C dvC/dt. When blocked, io = 0, iC = −iR, and vC decays with time constant (R + RC)C. Capacitor voltage stays continuous; output voltage can jump at firing.
Ideal SCRs use adequate gate drive, zero latching/holding thresholds and zero recovery time. No finite source inductance or overlap is modeled. This resolves teaching waveforms, not device ratings or a hardware gate-drive design.
Predict, test, explain
Predict what changing α from 0° to 60° does to the resistive-load mean voltage. Prepare the case, inspect the gate and current windows, then explain the result.
Reveal the explanation
Delayed firing removes part of the resistive conduction interval. The complete source-current waveform, rather than a cosine rule assumed for continuous inductive current, determines this result.
With an opposing DC load, compare a 5° gate window and a wide window at the same delay. Predict whether the source becomes eligible before the gate ends.
Reveal the explanation
A gate pulse can finish before the blocked load can accept current. A longer gate window can then initiate conduction when the source overtakes the load voltage. Once current is established, the gate ending does not interrupt it.
Prepare R‖C. Compare output-current RMS with resistor-current RMS and locate the largest charging pulse. Predict the effect of reducing RC; confirm that capacitor voltage remains continuous.
Reveal the explanation
The resistor sees iR = vo/R. The rectifier must also charge C, so its RMS current can be much larger. RC limits the charging pulse and dissipates RC iC²; it also slightly changes the voltage seen by R. A very small RC is not zero.
Power, stored energy and device currents
Positive input power flows from AC to the load; negative input power flows back to AC. In periodic steady state, mean inductor and capacitor powers are zero. The signed E-source power is E times mean series current.
Instantaneous power and stored energy
Stored energy
SCR-current waveforms
Anode-to-cathode current in amperes, using the device numbers in the circuit. Choose one device to inspect overlapping traces. The cursor is linked to the circuit; mean/RMS values below use the complete source period.
| Device | Full-period mean current | Full-period RMS current |
|---|
Source-current spectrum and power factor
Bars show RMS components of phase-U source current. Frequency labels use the complete repeating pattern. Distortion ratios use the complete waveform and the supply-frequency fundamental RMS, independently of the displayed bars.
Source-current spectrum and power factor
For the sinusoidal source, PF = P/S = DPF × DF. DPF = cos(φ₁); DF = fundamental-current RMS / complete source-current RMS. Ratios are undefined if their denominator is zero. A negative PF indicates net regeneration.
Diode comparison and analytical limits
The reference uses the same source, load, device drops and capacitor-branch resistance, with natural diode commutation. At α = 0° and a sufficiently long gate window, the SCR solution must coincide with this reference. The existing ideal R‖C diode filters have RC = 0 and are a different filter model.
| Vo,dc (V) | IR,dc (A) | Is,rms (A) |
|---|
The cosine formula requires continuous series current, successful scheduled commutations, no capacitor and zero source impedance. Constant device drops subtract n_d VF while the source path conducts. Inversion also requires a DC energy source and sustained positive current; α > 90° alone does not guarantee it.
Conventions, limitations and data
U, V and W name phase terminals; italic R names resistance. Current subscript R means the load resistor. The main R‖C current cards refer to that branch. All means, RMS values and spectra use one complete source period, not just the conduction interval.
Periodic steady state with ideal sinusoidal voltage sources. No startup, source impedance, finite commutation overlap, recovery, leakage, temperature or transformer model is included. The small charging resistor is the only extra element in the capacitor branch; it is not source resistance. Current peaks are model results, not safe device ratings.
When every bridge device is blocked, individual AC-to-DC device voltages require a common-mode or leakage model that is absent here. The displayed state describes complete current paths and actual device currents; it does not invent those floating terminal voltages.
Piecewise periodic solutions use bracketed switching events, stable linear-ODE convolution and quadrature split at those events and time constants. The laboratory checks current signs, Kirchhoff and branch laws, state continuity, and instantaneous and periodic power balances before accepting results. No arbitrary minimum L or C is used.
CSV uses SI units and a decimal point. Its event-enhanced grid is not uniform. At a jump, equal angles with limit_side = left/right give exact one-sided states. Source/phase current, complete output current, resistor current and capacitor-branch current have distinct columns. THD fields are dimensionless ratios; displayed THD is a percentage.
Optional technical references
STMicroelectronics · AN303 · Latching current
This separate laboratory follows the corresponding diode circuit, notation and assessment design. Its firing model is explicitly defined here.