Switch deliberately.
Protect the whole path.

Source and sink: compare both transitions

Model scope. The linear equivalent capacitance C_eq represents the insulated gate. The two resistances include driver output resistance and the gate path. These are gate-voltage transitions, not predicted drain/collector switching times; Miller charge, parasitic inductance, leakage, and device current are not simulated. The waveform is the exact periodic state of this RC model. [1]

An initial current boost is not a DC short circuit

Compare a step with and without C₁ in parallel with R₁. The gate is represented by C_eq = 5 nF; the drive step is 12 V. Both capacitors are initially discharged.

V_G is not V_GS

A floating source or emitter does not share the control return potential. Change the source potential and compare a ground-referenced driver with a driver referenced to the device.

Model scope. Voltage bookkeeping with an imposed source potential, not a physically self-consistent MOSFET operating-point calculation. Very negative V_GS values illustrate a wrong reference; they are not allowable gate voltages. A floating driver can use level shifting or galvanic isolation; they are not the same thing.

Trace the optocoupler and two inversion stages

With light present, the phototransistor drives Q₁ on. Q₁ pulls Q₃’s base low, so Q₃ turns off and R₃ pulls the gate high. Without light, Q₁ turns off, Q₃ turns on, and the gate is pulled low. This circuit uses a resistive pull-up and an active pull-down; it is not the complementary totem pole of the previous section.

Signal isolation is not a power supply. The output stage needs auxiliary energy referenced to its local source/emitter. The complete insulation barrier includes the auxiliary supply and layout. No voltage rating, creepage distance, or safety category is certified by this diagram.

Pulse transformers need flux reset

Model scope. Additional linear-core model: f = 50 kHz, N₁ = 20 turns, Aₑ = 50 mm², initial B = 0. Primary voltage is prescribed for three periods. A repeated unbalanced voltage causes flux drift; saturation and winding losses are not simulated. [1]

A short gate pulse may end before latching

The gate initiates conduction. It must provide adequate current while the anode current reaches the latching level I_L. Removing the gate is not a turn-off command for an already latched SCR.

Model scope. An additional constant-voltage RL reference isolates pulse-duration effects: 48 V source, 1.2 V SCR drop, I_L = 50 mA, I_GT = 50 mA, V_GK = 1.5 V, and a 2 ms gate window. The plotted anode current assumes uninterrupted conduction from zero. It is not an actual current trace after failed triggering or during gate gaps. [2]

Four ways to shape a trigger signal

Circuit-reading qualification. The pulse families above are functional descriptions. A capacitor connected from a base-drive node to return does not, by itself, form a series differentiator. Likewise, pulse extension and self-oscillation cannot be inferred from the mere presence of C or N₃: the actual connections, feedback polarity, reset path, and input waveform must be checked. No transistor-level simulation of those pulse generators is claimed.

Zero crossing → delay → pulse shaping → isolation

The markers identify timing only, not the output of a controlled bridge. Gate returns of different SCRs cannot simply be joined: their cathodes may be at different potentials. Each floating channel needs an appropriate reference and isolation arrangement.

Protect the gate without defeating the trigger

R_GK and C_GK name the external gate-to-cathode resistor and capacitor. Elsewhere, C_eq denotes the equivalent MOSFET/IGBT gate capacitance. These elements trade noise immunity against available trigger current and pulse shape. Their values must preserve reliable triggering while respecting the gate’s positive/negative voltage, current, and power limits. A shunt capacitor is not a substitute for correct power-terminal dv/dt control.

Follow the heat from junction to ambient

Model scope. Steady-state series thermal network for one device at imposed average loss. Temperatures do not feed back into electrical losses. Transient thermal impedance, airflow prediction, heat-sink geometry, and shared heat sinks are outside this model.

Shared initial benchmark: 25 W of loss, 25 °C ambient, and thermal resistances 0.4 / 0.2 / 1.5 K/W from junction to case, case to heat sink, and heat sink to ambient. It gives heat-sink / case / junction temperatures of 62.5 / 67.5 / 77.5 °C. Each laboratory has its own controls; these are initial comparison values, not a live link or a check of transient thermal impedance or safe operating area.

Compare the thermal benchmark in Power Semiconductors (selection and thermal model).

A capacitor changes dv/dt; a resistor changes damping

A series RC branch across a switch provides a transient current path. Parasitic inductance and stored charge can otherwise produce voltage peaks, ringing, unintended triggering, and EMI. Observe both capacitor voltage and voltage across the complete RC branch.

Model scope. Additional reduced RLC commutation model: a constant source feeds L_s, then the series RC branch after the switch opens. Initially v_C = 0 and i_L = I₀. The open switch sees v_sw = v_C + Ri. Device capacitance, body-diode clamping, and reverse recovery are omitted; this is not a complete converter or a component-selection algorithm. [3]

Clamping voltage depends on surge current

The protective device diverts current into a defined return path. Change the source resistance as well as its voltage: the same suppressor does not clamp at one invariant voltage. Negative surges distinguish unidirectional and bidirectional behavior.

Model scope. Hypothetical static curves and a rectangular surge feeding a high-impedance load. TVS: linear avalanche branch with a knee V_k and resistance r_d; reverse polarity of the unidirectional model uses a 0.7 V forward knee and 0.1 Ω. MOV: I = 1 mA · sign(V) · (|V|/V_ref)^α. Temperature, parasitics, aging, capacitance, and pulse-power limits are not simulated. This is not a matched-product comparison. [4]

Melting is not the same as complete interruption

Model scope. Prescribed current envelopes, not a fuse-selection simulation. Prospective current is a 50 Hz half-sine. Actual current follows it until the chosen melting time, then falls linearly to zero during the chosen arc time. Both times are inputs, not predictions from a fuse rating. The I²t values are exact integrals of these drawn curves. [5]

Compare curves, not just current ratings

Model scope. Stylized envelopes in the same axis orientation as a current-versus-time comparison, with a logarithmic time axis. They illustrate full-range versus short-circuit-only coordination; they are not manufacturer curves. “Coordinated” refers only to the plotted hypothetical envelopes, not to every fault or operating condition.

Crowbar: force a fault path, then disconnect it

A crowbar deliberately provides a low-impedance shunt after detecting overvoltage. Unlike a TVS, its objective here is to collapse the output and cause upstream disconnection, not to hold the output close to a precise clamping voltage.

Model scope. Coordination estimate with a high-impedance load, a 30 V trip threshold, a 1.2 V conducting SCR, an assumed 50 mA sustaining threshold, and a 1 ms prescribed arc. Pre-arcing I²t is treated as constant for this short-fault illustration. No output capacitor, source inductance, temperature feedback, or detailed SCR/fuse arc interaction is simulated. The timing plot ends at the 10 ms inspection deadline. Time zero is the onset of the imposed overvoltage. The total time includes detection/trigger delay, melting, and arcing.

Use each error to identify a missing distinction

24 questions, one correct answer each. The first attempt is recorded separately from practice. Revealing a solution without answering counts as consulted, not correct. This local record is for self-assessment, not an academic grade.